This invention relates to the control of solid-state image sensors used, for example, in a video camera or the like.
When a subject is photographed and a standard television signal is formed in a video camera, ordinarily the exposure time of an image sensor incorporated within the video camera is set to be the same as a time (one field interval) equivalent to one period of the periods (field periods) of a vertical synchronizing signal of the standard television signal (this is well-known field reading).
However, depending upon the subject to be photographed, there are cases where it is desired to make the exposure time longer than one field interval because the illumination or the subject is inadequate, by way of example. Consequently, a method (well-known frame reading) has been proposed in which the exposure time of the image sensor is set to a time equivalent to two periods of the field periods by specially contriving the timing at which the signal is read from the image sensor, and by using an image memory.
Frame reading will be described with reference to FIGS. 1 through 3.
FIG. 1 is a block diagram illustrating the construction of the circuitry of a video camera for performing frame reading. The circuitry includes a CCD 1 for performing a photoelectric conversion, a CCD driver circuit 2 for driving the CCD 1, a synchronizing signal generating circuit 3 for generating various synchronizing signals necessary in order to form a standard television signal, a timing control signal 4 for controlling the timing of the control of the exposure time based upon a signal from the synchronizing signal generating circuit 3, a signal processing circuit 5 for forming a luminance signal (Y) and color-difference signals (R-Y, B-Y) from the signal outputted by the CCD 1, an A/D converting circuit 6 for converting an analog output signal from the signal processing circuit 5 into a digital signal, an image memory 7 for storing and outputting the output signal from the A/D converting circuit 6 in dependence upon a signal from the timing control circuit 4, a D/A converting circuit 8 for converting the digital output from the image memory 7 into an analog signal, and an encoder circuit 9 for forming the standard television signal from a luminance signal (Y') and color difference signals [(R-Y)', (B-Y)'] outputted by the D/A converting circuit 8.
FIG. 2 is a plan view of the CCD 1 and schematically illustrates the structure of a so-called interline transfer-type CCD. Numeral 10 denotes a sensor which performs a photoelectric conversion, 11 a vertical transfer register, 12 a horizontal transfer register, and 13 an output amplifier.
FIG. 3 is a timing chart of signals applied to various portions of the CCD, output signals from various portions of the CCD, and a signal generated by sensor portion 10 of the CCD 1, all at the time of frame reading. As mentioned above, exposure time is twice one field interval in frame reading. In FIG. 3, V.sub.D represents a vertical synchronizing signal, and .phi.ROG represents a read-out pulse for transferring the charge, which has accumulated in the sensor portion 10, to the vertical transfer register 11.
As illustrated in FIG. 3, the .phi.ROG pulse is applied to the CCD 1 only once in two field intervals. As a result, after the charge has accumulated for about two fields, with time t.sub.0 serving as the starting point, the charge in the sensor portion 10 is transferred to the vertical transfer register 11 at time t.sub.1. Thereafter, the charge is transferred to the horizontal transfer register 12 and outputted to the signal processing circuit 5 via the output amplifier 13.
In one field interval (interval B1) which immediately follows the application of the .phi.ROG pulse, the charge stored in the sensor portion 10 from time t.sub.0 to time t.sub.1, namely the charge which has accumulated for about two fields, is outputted as an image signal (SB1) via the output amplifier 13. In the next field interval (interval B2), however, the .phi.ROG pulse is not applied and therefore a blank signal is outputted.
Accordingly, immediately after the .phi.ROG pulse is applied to the CCD 1, the A/D converting circuit 6 is driven by the timing control circuit 4 shown in FIG. 1 so that the electric charge stored for about two field intervals outputted by the signal processing circuit 5 is stored in the image memory 7 and outputted to the D/A converting circuit 8 simultaneously (interval B1). Then, in the next field interval (interval B2), the signal stored in the image memory 7 for interval B1 is outputted to the D/A converting circuit 8 (interval B2). As a result, the D/A converting circuit 8 outputs the same signal for two consecutive fields, as illustrated in FIG. 3.
However, in a case where an exposure time greater than one field interval T is required, as when illumination of the subject is inadequate, in the example of the prior art described above, the exposure time of the sensor portion 10 becomes twice the field interval at a stroke if a change is made from a state in which the .phi.ROG pulse is applied every field to the state in which this pulse is applied every two fields. As a result, exposure time cannot be varied finely in conformity with the brightness of the subject.